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In September of 2012 JEDEC released preliminary standards for DDR4. DDR4 has significant increases in performance as well as improved reliability and reduced power compared to the last generation of DRAM technology. DDR4 will have double the speed and memory density, and will use 20% less power representing significant achievement relative to past DRAM technologies. DDR4 is able to achieve lower power consumption by dropping voltages from 1.5V as in DDR3 to 1.2V while increasing the performance factor to 2,133 MT/sec to start with future goals of 3,200 MT/sec.
One of the most significant changes is the proposed requirement to establish the reference voltage or V center used for compliance testing using a variable approach. For DDR3, this value was fixed at 750 mV. The new approach involves making multiple acquisitions of the DQ and a DQS Write burst. The largest to smallest voltage value for each is then measured and an average created using a simple formula. This then becomes the DQ voltage reference for centering and making reference measurements using an eye diagram.
Following the lead of many serial standards, DDR4 will now incorporate a statistical jitter measurement approach for speeds greater than 2,133. For speeds under 2,133, all jitter will be assumed to be deterministic jitter or DJ. For 2,133 and above, tests will look at both DJ and random jitter or RJ. To date, many of the timing parameters for jitter have not been published, but designers should be aware that jitter testing will be a requirement. One benefit of expanded jitter testing in DDR4 is that should devices fail to meet jitter requirements, the test and measurement vendor community offers robust jitter decomposition tools that can help isolate the source of problems.
DDR4 SLOTS
DDR4-1600 1600 Mb/s/pin 800 MHz
DDR4-1866 1866 Mb/s/pin 933 MHZ
DDR4-2133 2133 Mb/s/pin 1066 MHz
DDR4-2400 2400 Mb/s/pin 1200 MHz
DDR4-2667 2667 Mb/s/pin 1333 MHz
DDR4-3200 3200 Mb/s/pin 1600 MHz
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