DDR sdram memory

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 256mb               512MB                 1GB                    
DDR (Double Data Rate) SDRAMs increased the memory data rate performance by increasing clock rates, bursting of data and transferring two data bits per clock cycle (See Table 1). DDR SDRAMs burst multiple memory locations in a single read or single write command. A read memory operation entails sending an Activate command followed by a Read command. The memory responds after its latency with a burst of two, four, or eight memory locations at a data rate of two memory locations per clock cycle. Therefore, four memory locations are read from or written to in two consecutive clock cycles.
DDR SDRAMs have multiple banks to provide multiple interleaved memory access, which increases memory bandwidth. A bank is one array of memory, two banks are two arrays of memory, four banks are four arrays of memory, etc (See Figure 3). Four banks require two bits for bank address (BA0 & BA1).
Note that the power required by the DDR SDRAM is related to the number of banks with open rows. More open rows require more power and larger row sizes require more power. Therefore, for low power applications one should open only one row at a time in each bank and not have multiple banks each with open rows.

Chip sizes:  128mb ,256mb ,512mn ,1gb

                                                 DDR   SLOTS

DDR SDRAM                      Data Rate                   Memory Clock

DDR-266                          266 Mb/s/pin                      133 MHz
DDR-333                          333 Mb/s/pin                      166 MHz
DDR-400                          400 Mb/s/pin                      200 MHz